1. Field of the Invention
The present invention relates to VISS (VHS Index Search System) signal detection circuits, and more particularly, to a VISS signal detection circuit detecting a VISS signal recorded on a magnetic tape in a VTR (Video Tape Recorder).
2. Description of the Background Art
In a VHS type VTR, there is provided a feature for a user to write desired data on a magnetic tape to facilitate retrieval of data in a recorded tape. More specifically, a VISS signal having two types of duties corresponding to 0 and 1 is recorded on a magnetic tape taking advantage of the control track used in servo control. This VISS signal indicates the index code to be used mainly for head position detection.
A signal recorded on a magnetic tape is read out by a control head. The level of the read out signal varies according to the moving speed of the magnetic tape. When the speed of the magnetic tape is low as at the time of initiating reproduction, the amplitude of the signal read out by the control head is small. In contrast, when the speed of the magnetic tape is high as in fast-forwarding, rewinding, fast-forward reproduction, and rewind reproduction, the amplitude of the read out signal is great. Therefore, the amplitude of the VISS signal read out by the control head depends upon the tape speed.
FIG. 9 is a circuit diagram showing a structure of a conventional VISS signal detection circuit that can detect a VISS signal for both the cases of a high speed and a low speed tape. Referring to FIG. 9, a signal recorded on a magnetic tape is read out by a control head 1. A control head signal CH from control head 1 is applied to a VISS signal detection circuit 2. Control head signal CH is biased by a voltage Vbias by a bias power supply 3. Control head signal CH is amplified by a differential amplifier 4. The gain (amplification factor) of differential amplifier 4 is determined by resistors 5 and 6 and a resistor array 7. Resistor array 7 is formed of a plurality of resistors having various resistances. A switch circuit 8 switches the resistor in resistor array 7 according to the tape speed. More specifically, switch circuit 8 functions to switch the resistor in resistor array 7 so that the gain of differential amplifier 4 becomes greater when the tape speed is low and smaller when the tape speed is high. Therefore, the amplitude of a signal APout output from differential amplifier 4 is constant as shown in FIG. 10 regardless of the tape speed. Signal APout output from differential amplifier 4 includes erase noise 10 in addition to a signal VISS 9 of a large amplitude. Erase noise 10 is the noise that remains when the VISS signal is rewritten to 0 from 1 or vice versa. A VISS signal 9 higher than bias voltage Vbias is detected by a comparator 11 shown in FIG. 9. A VISS signal lower than bias voltage Vbias is detected by a comparator 12. Therefore, comparator 11 is supplied with a reference voltage Vrefh lower than the peak value of VISS signal 9 and higher than bias voltage Vbias. Similarly, comparator 12 is supplied with a reference voltage Vrefl. An output signal CPouth from comparator 11 is applied to the set terminal of a RS flip-flop circuit 13. An output signal CPout1 of comparator 12 is applied to the reset terminal of RS flip-flop circuit 13. Therefore, detection signal Dout from RS flip-flop 13 attains an H level (logical high) when output signal APout exceeds reference voltage Vrefh and an L level (logical low) when output signal APout exceeds reference voltage Vref1. This signal Dout is the detection signal of a VISS signal. When the ratio of a term t1 to term t2 (duty ratio) is approximately 60%, recognition is made of 0. When the duty ratio is approximately 25%, recognition is made of 1. By recording such a VISS signal by a predetermined data pattern (for example, 011 . . . 110) on a magnetic tape, head position detection can be facilitated by detecting this VISS signal.
By switching the gain of differential amplifier 4 according to the tape speed, the amplitude of the signal read out by control head 1 can be made constant substantially. However, the amplitude of this signal varies slightly as shown in FIG. 11 even when the tape speed is constant. Although all the peaks of VISS signal 9 can be detected by setting reference voltage Vrefh of comparator 11 low and reference voltage Vrefl of comparator 12 high, there is a possibility of erroneous detection of erase noise 10 as a peak of VISS signal 9. In contrast, if reference voltage Vrefh of comparator 11 is set high and reference voltage Vrefl of comparator 12 is set low, there is a possibility of not detecting all the peaks of VISS signal 9 although no erase noise 10 will be detected erroneously. There will be no problem if reference voltages Vrefh and Vref1 are set intermediate the peak of VISS signal 9 and the peak of erase noise 10. However, this setting is not so easy since the amplitude of erase noise 10 differs depending upon the tape speed and the like.
When VISS signal detection circuit 2 of FIG. 9 is employed, resistor array 7 must be externally controlled by a microcomputer and the like. However, it is difficult to implement task sharing with another real time task since the microcomputer will exclusively carry out this detection task during the VISS signal detection.
In view of the foregoing, an object of the present invention is to provide a VISS signal detection circuit that can properly detect a VISS signal.
Another object of the present invention is to provide a VISS signal detection circuit that can always detect a VISS signal properly even when the tape speed changes.
A further object of the present invention is to provide a VISS signal detection circuit that can detect a VISS signal properly even when the tape speed is constant.
Still another object of the present invention is to provide a VISS signal detection circuit that does not erroneously detect erase noise as a VISS signal.
A still further object of the present invention is to provide a VISS signal detection circuit that does not require external control.
According to an aspect of the present invention, a VISS signal detection circuit detecting a VISS signal recorded on a magnetic recording medium includes a plurality of first comparators, a plurality of second comparators, a select circuit, and an output circuit. The plurality of first comparators have a threshold value differing from each other. Each first comparator compares the level of the VISS signal with its threshold value to supply an output signal when the level of the VISS signal is higher than the threshold value. The plurality of second comparators have a threshold value differing from each other. Each second comparator compares the level of the VISS signal with its threshold value to supply an output signal when the level of the VISS signal is lower than the threshold value. The select circuit selects the output signal from the comparator that has the second highest threshold value out of the first comparators supplying an output signal at the prior comparison, and the output signal from the comparator having the second lowest threshold value out of the second comparators supplying an output signal at the prior comparison. The output circuit provides a detection signal that is driven to a first level in response to one output signal from the select circuit and that is driven to a second level in response to the other output signal from the select circuit.
When the peak level of the VISS signal is detected in the above VISS signal detection circuit, the level of the threshold value to detect the next VISS signal is set slightly lower or higher than that detected peak level. Since the threshold value is reset to an optimum level every time a VISS signal is detected, a VISS signal can be detected reliably without erroneous detection of the erase noise.
Preferably, the VISS signal detection circuit further includes an amplifier. The amplifier amplifies by a constant gain the VISS signal to be applied to the plurality of first and second comparators. Therefore, it is not necessary to externally control the gain of the amplifier by a microcomputer and the like.
Preferably, the select circuit includes a plurality of first latch circuits, a plurality of second latch circuits, a first logic circuit, a plurality of third latch circuits, a plurality of fourth latch circuits, and a second logic circuit. The plurality of first latch circuits are provided corresponding to the plurality of first comparators. Each first latch circuit latches an output signal from a corresponding first comparator. The plurality of second latch circuits are provided corresponding to the plurality of fist latch circuits. Each second latch circuit latches an output signal from a corresponding first latch circuit. The first logic circuit selects the output signal from the comparator having the second highest value among the first comparators supplying an output signal at the prior comparison in response to the plurality of second latch circuits. The plurality of third latch circuits are provided corresponding to the plurality of second comparators. Each third latch circuit latches an output signal from a corresponding second comparator. The plurality of fourth latch circuits are provided corresponding to the plurality of third latch circuits. Each fourth latch circuit latches the output signal from a corresponding third latch circuit. The second logic circuit selects the output signal from the comparator having the second lowest threshold value among the second comparators supplying an output signal at the prior comparison in response to the plurality of fourth latch circuits.
In the above VISS signal related circuits, the maximum peak level of the VISS signal in the prior comparison by the first comparator is retained at the second latch circuit. Therefore, the threshold value of the current comparison is set slightly lower than the threshold value level of the prior comparison. The smallest peak level of the VISS signal at the prior comparison is retained in the fourth latch circuit. Therefore, the threshold value level of the current comparison is set slightly higher than the threshold value level of the prior comparison.
Preferably, the output circuit includes a flip-flop circuit. The flip-flop is set in response to one output signal from the select circuit and reset in response to the other output signal of the select circuit.
Preferably, the VISS signal detection circuit further includes a first switching element and a second switching element. The first switching element is connected between the input terminal of the first comparator having the lowest threshold value out of the plurality of first comparators and the input terminal of the first comparator having the second lowest threshold value out of the plurality of first comparators, and is turned on in response to the output signal from the first comparator having the lowest threshold value. The second switching element is connected between the input terminal of the second comparator having the highest threshold value out of the plurality of second comparators and the input terminal of the second comparator having the second highest threshold value out of the plurality of second comparators, and is turned on in response to the output signal from the second comparator having the highest threshold value.
When the first comparator having the lowest threshold value does not supply an output signal in the above VISS signal detection circuit, the VISS signal is supplied only to the first comparator that has the lowest threshold value, and is not supplied to the other first comparators. When the second comparator having the highest threshold value does not supply an output signal, the VISS signal is supplied only to the second comparator having the highest threshold value, and is not supplied to the other second comparators. More specifically, the first switching element is turned on only during the period where the first comparator having the lowest threshold value supplies an output signal, and the second switching element is turned on only during the period where the second comparator having the highest threshold value supplies an output signal. Therefore, the input capacitance can be suppressed at a low level even when there are many first and second comparators.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.